There is an ever increasing demand for power conversion and regulation circuitry to operate with increased efficiency and reduced power to accommodate the continuous reduction in size of electronic portable devices. Many times these devices are battery powered, and it is desirable to utilize as little power as possible to operate these devices so that the battery life is extended. Switching regulators have been implemented as an efficient mechanism for providing a regulated output in power supplies. One such type of regulator is known as a switching regulator or switching power supply, which controls the flow of power to a load by controlling the on and off duty-cycle of one or more high-side switches coupled to the load. Many different classes of switching regulators exist today.
One type of switching regulator is known as a synchronous switching regulator. In a synchronous switching regulator, an inductor is used to maintain current flow that is switched from two separate sources. The two sources can include a high-side switch, such as a high-side field-effect transistor (FET), and a low-side switch, such as a low-side FET and a freewheeling diode. Once the high-side FET is turned off, magnetic power stored in the inductor dissipates to force current through the inductor by changing the voltage of the inductor source node to negative relative to ground. The freewheeling diode thus conducts current from ground to the inductor after the high-side has been turned off and before the low-side FET has been turned on. In this way, current continuously flows through the inductor in the times between activation of the high-side and the low-side switches.
Switching regulator circuit designers need to be conscientious of electromagnetic interference (EMI) emissions that result from current flow within a given switching regulator circuit. One source of EMI emissions in a switching regulator results from the rapid changes in input current (di/dt) as the power FET is activated and the rapid decay of current as the power FET is deactivated. When the gate voltage of a power FET reaches its threshold voltage, current flows through the power FET and can create EMI emissions. When the gate voltage of the power FET increases rapidly above the threshold voltage, the EMI emissions resulting from the rapid changes in input current flow through the FET are often too large in magnitude to meet acceptable design criteria. A solution to this problem of unacceptable EMI emissions is to slow the increase of the gate voltage of the power FET, such as by adding capacitance to the gate relative to the source of the power FET. This results in a slower increase of input current, and thus reduces the EMI emissions from the switching regulator.
FIG. 1 depicts a graph 10 of time versus voltage demonstrating a relative rate-of-increase of a gate voltage of a power FET in a switching regulator. The power FET to which the graph 10 models has a threshold voltage VT (depicted as about 2 volts in the example of FIG. 1) at which the power FET begins to activate. It is at this point in which current begins to flow from the drain to the source of the power FET. The range of voltage from the threshold voltage VT to a voltage VF at which the power FET is fully activated (about 4 volts in the example of FIG. 1) is depicted as an activation region 12.
A dashed line 14 (denoted “fast” in a legend 16 of the graph 10) represents a more rapid rate-of-increase (i.e., greater slope) of the gate voltage of the power FET. As the gate voltage increases at a rapid rate, the rate of change of input current flowing through the power FET will be very high, resulting in unacceptable levels of EMI emissions. A dashed line 18 (denoted “slow” in the legend 16 of the graph 10) represents a slower rate-of-increase (i.e., smaller slope) of the gate voltage of the power FET. As the gate voltage increases at a slower rate, the rate of change of the input current flowing through the power FET will be smaller, resulting in acceptable levels of EMI emissions.
A different problem, however, results from the slower increase of the gate voltage represented by the dashed line 18. Because the gate voltage corresponding to the dashed line 18 increases at a slower rate, it takes a longer period of time for the gate voltage to reach the threshold voltage VT. In the above example of the synchronous switching regulator, this means that the freewheeling diode is conducting current through the inductor for a longer period of time than if the gate voltage was increased at the faster rate. Because the magnetic field of the inductor collapses to maintain the freewheeling diode current while the power FET is off, the switching regulator experiences a loss of power while the freewheeling diode is conducting current. Thus, the dashed line 18 has a corresponding power loss below the activation region 12 that is greater than the dashed line 14. This loss of power of the switching regulator is represented in the graph 10 by a power loss region 20.
In addition to the power loss represented by the power loss region 20, the switching regulator also loses power after the power FET has become fully activated (i.e., conductive loss). While the gate voltage is increasing from the fully activated voltage VF to a maximum voltage VMAX (depicted as 10 volts in the example of FIG. 1), the power FET acts as a variable resistor between the drain and the source. At lower voltage levels greater than the fully activated voltage VF, the drain-to-source resistance RDSon of the power FET is greater than it is at the maximum voltage VMAX. Thus, the total amount of resistance over time (dr/dt) is inversely proportional to the amount of time it takes for the gate voltage to reach the gate maximum voltage VMAX. For example, the dashed line 14 experiences a smaller RDSon over time than the dashed line 18. Since resistive loads generate power loss in the form of heat, the dashed line 18 has a corresponding power loss that is greater than the dashed line 14 above the fully activated voltage VF. This loss of power is represented in the graph 10 by a power loss region 22.
The graph 10 of FIG. 1 thus demonstrates two separate ways in which to activate a power FET in a switching regulator. One way is to increase the gate voltage of the power FET rapidly, resulting in unacceptable levels of EMI emissions. The other way is to increase the gate voltage of the power FET slowly, resulting in undesired power loss. Thus, the two ways of activating a power FET in a switching regulator are subject to competing design constraints.